1. Field of the Invention
This invention relates to the field of memory circuitry. More particularly, this invention relates to memory circuitry including write assist mechanisms that seek to make it easier to overcome the feedback within a bit cell when seeking to change a bit value stored within a bit cell.
2. Description of the Prior Art
It is known to provide memory circuitry with write assist mechanisms which serve to lower the power supply voltage to bit cells which are to be written. Lowering the power supply voltage has the result of making it easier to overcome the feedback within a bit cell which seeks to maintain a current bit cell value. There are various problems with known write assist circuitry. The write assist circuitry should provide accurate control of the power supply voltage to the bit cells to be written such that the changing of a bit value is made easier, but there is not an undue risk of bit values being lost as the power supply voltage falls below a level needed by the bit cells to retain their bit values. This accurate control of the power supply voltage during write needs to occur across a wide range of manufacturing variation and operational conditions to which the memory circuitry may be subject. Furthermore, the dynamic current consumption associated with the write assist circuitry should be low in order to keep the current consumption of the memory circuitry as a whole at a desirably low level. It is also desirable that the write assist circuitry should have a low static current consumption when it is not in use and write operations are not taking place. Furthermore, the write assist circuitry should be able to accurately maintain a power supply voltage to the bit cells to be written when operating with bit cell arrays of varying different sizes as may be produced in a compiled memory. A memory may be compiled to have significantly different array sizes depending upon the target requirements and it is desirable that the write assist circuitry should be able to operate satisfactorily with arrays of bit cells of varying sizes without requiring significant modification to the write assist circuitry.